1. Field of the Invention
The present invention relates to a circuit and a method for temperature tracing of devices including an element of chalcogenic material, in particular of phase change memory devices.
2. Description of the Related Art
As is known, phase change memory devices comprise storage elements made of a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct electrical properties associated with each phase. For example, these materials may change between an amorphous disordered phase and a crystalline, or polycrystalline, ordered phase. A material property that may change and provide a signature for each phase is the material resistivity, which is considerably different in the two states.
Specific materials that may be suitably used in phase change cells are alloys of elements of the VI group of the periodic table as Te or Se, also called chalcogenides or chalcogenic materials. Therefore, hereinafter, the term “chalcogenic materials” is used to indicate all materials switcheable between at least two different phases where they have different electrical properties (resistances) and include thus the elements of the VI group of the periodic table and their alloys.
The presently most promising chalcogenide is an alloy of Ge, Sb and Te (Ge2Sb2Te5) which is already widely used for storing information in overwritable optical disks.
As indicated, for microelectronics applications, the interesting parameter is resistivity that varies of two or more orders of magnitude when the material transforms from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. Furthermore, in the amorphous state, the resistivity depends heavily from temperature, with resistivity changes of one order of magnitude every 100° C., with a similar behavior to P-type semiconductors.
Phase change may be obtained by locally increasing the temperature. Under 150° C., both phases are stable. Over 200° C., nucleation of crystallites is fast and if the material is kept to the crystallization temperature for a sufficient time, it changes phase and becomes crystalline. In order to change the phase back to the amorphous state, the chalcogenide temperature is brought over the melting point (about 600° C.) and rapidly reduced.
From an electrical point of view, it is possible to reach both critical temperatures (crystallization and melting temperatures) using an electric current flow through a resistive electrode in contact or close proximity with the chalcogenic material and heating the material by Joule effect.
A phase-change storage element 1 based on the above is shown in FIG. 1, and comprises a resistive electrode forming a heater 2 and a chalcogenic region 3. The chalcogenic region 3 is generally in the crystalline state to allow good current flow. A portion of the chalcogenic region 3 is in direct contact with the heater 2 and forms a phase change portion 4.
By passing an electrical current of suitable value through the heater 2, it is possible to selectively heat the phase change portion 4 to the crystallization or melting temperatures and cause a phase change.
FIG. 2 shows the plots of the required temperature versus time when a phase change from the crystalline to the amorphous state is desired (curve A) and a phase change from the amorphous to the crystalline state is desired (curve B). Tm indicates the melting temperature and Tx indicates the temperature at which crystallization begins. As shown, amorphization requires a short time (reset pulse) but a high temperature; furthermore the material should be cooled in a very short time (t1) to maintain the atomic disorder and avoid recrystallization of the material. Crystallization requires a longer time t2 (also called set pulse) to allow nucleation and crystal growing.
The state of the chalcogenic region 3 may be read by applying a sufficiently small voltage so as not to cause a sensible heating and measuring the current passing through it. Since the current is proportional to the conductance of the chalcogenic material, it is possible to discriminate between the two states.
In practice, a phase-change storage element 1 can be considered as a resistor which conducts a different current according to its phase. In particular, the following convention is adopted: a phase-change storage element 1 is defined as “set” when, once appropriately biased, it conducts a detectable current (this condition may be associated to a logic condition “1”), and as “reset” when, in the same biasing conditions, it does not conduct current or conducts a much lower current than a cell that is set (logic condition “0”).
The use of phase-change storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged in rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a phase-change storage element and a selection element, such as an MOS transistor or a diode.
For example, FIG. 3 shows a memory array 8 formed by a plurality of memory cells 10 arranged along rows and columns and connected to bit lines 11 (parallel to the columns of the memory array 8) and word lines 12 (parallel to the rows of the memory array 8).
Each memory cell 10 is formed by a memory element 15 having the basic structure of the phase-change storage element 1 of FIG. 2 and a selection element 16 formed by an NMOS transistor.
In each memory cell 10, the gate terminal of the NMOS transistor 16 is connected to the respective word line 12 having address WLn−1, WLn, . . . , the source terminal (during normal operation of the memory array 8, namely during reading or setting and resetting operations) is connected to a ground region 18, and the drain terminal is connected to a first terminal of the respective memory element 15. A second terminal of the memory element 15 is connected to a respective bit line 11 having address BLn−1, BLn, BLn+1, . . .
In the memory array 8 it is possible to program or read a single memory cell 10 by appropriately biasing the bit line 11 and the word line 12 connected thereto. All the bit lines 11 and all the word lines 12 that are not addressed must be grounded.
In particular, for selecting the cell 10 connected to word line 12 having address WLn−1 and bit line 11 having address BLn−1, appropriate voltages are applied to line BLn−1 and to line WLn−1 to have a first voltage V1 at one terminal of the memory element 15 and a second voltage V2 at a second terminal of memory element 15.
When cell 10 is to be written, the cell is fed with a current pulse I the length and amplitude whereof depend on the set or reset operation desired. FIG. 4 shows indicatively the length and amplitude of the writing pulse IS and IR in the two cases.
Since, as above said, heating of a chalcogenic element causes a phase transition by the Joule effect, when the storage element is flown by a current, there is a strict relationship among temperature, current and material state.
In particular, FIG. 5 shows the change in resistance as a function of the temperature and current. In particular, FIG. 5 shows three curves C, D and E obtained at temperatures T1, T2 and T3, wherein T1<T2<T3. In FIG. 5, IS1, IS2 and IS3 are the current values at which a cell 10 changes from the reset to the set state respectively at temperatures T1, T2, T3 and IR1, IR2 and IR3 are the current values at which a cell 10 changes from the set to the reset state respectively at temperatures T1, T2, T3.
As may be seen, the resistance R of a chalcogenic element is strongly dependent on the temperature in the amorphous (reset) state (high resistance portions of the curves) and is scarcely variable along with temperature in the crystalline (set) state (low resistance portions of the curves).
Furthermore, a set operation carried out at temperature T1 requires a higher current (IS1) than a set operation carried out at temperature T3 (IS3). Moreover, a reset operation carried out at temperature T1 requires a higher current (IR1) than a set operation carried out at temperature T3 (IR3). The little difference between the maximum set current IS1 and the minimum reset current IR3 is however problematic, as below explained.
In the absence of any information on the temperature, in order to ensure writing of a cell in a required temperature range (thus including the minimum temperature of the range, e.g., T1), the write current IS must be set equal to the maximum value required (in the example, IS1).
However, selecting a fixed, predetermined write current value IS1, involves the risk that the write current is too close or even exceeds the minimum writing current to bring the cell in the reset state (here, IR3). In presence of a high temperature, a set operation carried out with current IS1 could even cause a reset of the cell.
Thus, the writing operation is hardly controllable.
Furthermore, if the reset current IR in the required temperature range is a fixed value, this should be selected not lower than IR1 to ensure reset of the cell in all conditions, also at low temperature. However, the application of a high current value such as IR1 can cause, at a high temperature, a over-resetting of the cell.
Moreover, since there is a direct proportionality between the duration of the set pulse and the amplitude of the reset pulse, using the maximum current IR3 during the reset operation implies increasing the set time tS during the set operation. This increase would cause an unacceptable increase of the set time and thus in the requirements regarding the device writing speed.